恶补 CPU 知识之 Cache 和 TLB

即是知识回顾,也是最近学到知识的拓展延伸。 ARMv6 Manual: “The only architecturally-guaranteed way to invalidate all aliases of a physical address from a VIPT instruction cache is to invalidate the entire instruction cache.” Cache 的基本情况 Cache 也就是缓存,作为高速的 CPU 和低速的...

2024 Feb 18 Â· 6 min Â· vaaandark